ADT7476A
http://onsemi.com
4
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(T
A
= T
MIN
 to T
MAX
, V
CC
= V
MIN
 to V
MAX
, unless otherwise noted) (Note 1)
Parameter
Unit
Max
Typ
Min
Conditions
Analog-to-Digital Converter (Including MUX and Attentuators)
Input Resistance
For V
CCP
 Channel
For All Other Channels
70
70
200
114


kW
Fan RPM-to-Digital Converter
Accuracy
0癈 ?T
A
?70癈
40癈 ?T
A
?+120癈




?
?0
%
Full-Scale Count


65,535
Nominal Input RPM
Fan Count = 0xBFFF
Fan Count = 0x3FFF
Fan Count = 0x0438
Fan Count = 0x021C




109
329
5,000
10,000




RPM
Open-Drain Digital Outputs, PWM1 TO PWM3, XTO
Current Sink, I
OL


8.0
mA
Output Low Voltage, V
OL
I
OUT
 = 8.0 mA


0.4
V
High Level Output Current, I
OH
V
OUT
 = V
CC

0.1
20
mA
Open-Drain Serial Data Bus Output (SDA)
Output Low Voltage, V
OL
I
OUT
 = 4.0 mA


0.4
V
High Level Output Current, I
OH
V
OUT
 = V
CC

0.1
1.0
mA
SMBus Digital Inputs (SCL, SDA) (Note 2)
Input High Voltage, V
IH
2.0


V
Input Low Voltage, V
IL


0.8
V
Hysteresis

500

mV
Digital Input Logic Levels (TACH Inputs)
Input High Voltage, V
IH
Maximum Input Voltage
2.0

5.5
V
Input Low Voltage, V
IL
Minimum Input Voltage
0.3

0.8
V
Hysteresis

0.5

V p-p
Digital Input Logic Levels (THERM
) ADTL+
Input High Voltage, V
IH
0.75 ?V
CCP


V
Input Low Voltage, V
IL


0.8
V
Digital Input Current
Input High Current, I
IH
V
IN
 = V
CC

?

mA
Input Low Current, I
IL
V
IN
 = 0

?

mA
Input Capacitance, C
IN

5.0

pF
Serial Bus Timing   (See Figure 2)
Clock Frequency, f
SCLK
10

400
kHz
Glitch Immunity, t
SW


50
ns
Bus Free Time, t
BUF
4.7


ms
SCL Low Time, t
LOW
4.7


ms
SCL High Time, t
HIGH
4.0

50
ms
SCL, SDA Rise Time, t
r


1,000
ns
SCL, SDA Fall Time, t
f


300
ms
Data Setup Time, t
SU;DAT
250


ns
Detect Clock Low Timeout, t
TIMEOUT
Can be Optionally Disabled
15

35
ms
1.  All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are T
A
= 25癈 and represent a parametric norm.
Logic inputs accept input high voltages up to V
MAX
, even when the device is operating down to V
MIN
. Timing specifications are tested at logic
levels of V
IL
= 0.8 V for a falling edge, and V
IH
= 2.0 V for a rising edge.
2.  SMBus timing specifications are guaranteed by design and are not production tested.
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